Intellectual Property (Publications, Books, Patents) :
Books: 5
1. Natak Samagra (Collection of plays) – publisher Saptarshi Prakashan 2010
2. Aja Kahini (Collection of Plays) – Kalabhrit Publications 2012
3. Rajar Chithi & Others (Collection of Plays) – Pratibhas Publications 2016
4. Koutuki Dosh (Collection of Plays) – Naba Grantha Kutir 2018
5. Dwapar Katha – The Stories of Mahabharata (in Print) – Harper Collins India (2023 fall release)
Theatre Journals and Magazines:
– Dramatist (Dramatist Guild of America publication)
– SAS (published in Kolkata)
– Bratyojon Natyapatra
– Bahurupee magazine
– Minerva Natya Charcha
– Natyapatra
– Antorjatik Pathshala
– Krittibash
– Baitalik
– many others
Patents: 8
Technical Publications: 38 (22 Conf, 16 Journal)Publications List: Sudipta Bhawmik
Journal Publications
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2015; 34(1):136-149.
DOI:10.1109/TCAD.2014.2365097
On improving test quality of scan-based BIST
Huan-Chih Tsai, Kwang-Ting Cheng, S. Bhawmik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 09/2000; 19(8-19):928 – 938.
A BIST scheme for RTL circuits based on symbolic testability analysis
I. Ghosh, N.K. Jha, S. Bhawmik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 02/2000;
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access
Mechanism (TAM) Switch.
Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik
Journal of Electronic Testing 01/2002; 18:475-485. DOI:10.1023/A:1016549725661 · 0.43 Impact Factor
Efficient test-point selection for scan-based BIST
Huan-Chih Tsai; Kwang-Ting Cheng; Chih-Jen Lin; Bhawmik, S.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Year: 1998, Volume: 6, Issue: 4 Pages: 667 – 676,
Integration of partial scan and built-in self-test.
Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik
Journal of Electronic Testing 01/1995; 7:125-137
DFT Expert: designing testable VLSI circuits
S. Bhawmik, P. Palchaudhuri
IEEE Design and Test of Computers 11/1989; 6(5-6):8 – 19.
Design of testable VLSI circuits with minimum area overhead
P.R. Chalasani, S. Bhawmik, A. Acharya, P. Palchaudhuri
IEEE Transactions on Computers 11/1989; 38(10-38):1460 – 1462.
Expert system to configure global design for testability structure in a VLSI circuit
Sudipta Bhawmik, Parimal Palchaudhuri
Microprocessors and Microsystems 09/1989; 13(7-13):462-472.
Selecting test methodologies for PLAs and random logic modules in VLSI circuits — an
expert systems approachSudipta Bhawmik, V.K. Narang, Parimal Pal Chaudhuri
Integration the VLSI Journal 09/1989; 7(3-7):267-281
KIDLAN: A hardware description language
Anurag Acharya, Sudipta Bhawmik, C.R.K. Prasad, P. Palchaudhuri
Microprocessing and Microprogramming 03/1989; 26(1):1–13.
Efficient characterisation of cellular automata
Das, A.K.; Ganguly, A.; Dasgupta, A.; Bhawmik, S.; Chaudhuri, P.P.
Computers and Digital Techniques, IEE Proceedings E Year: 1990, Volume: 137, Issue: 1 Pages: 81 – 87Conference Proceedings Publications
At-speed interconnect testing and test-path optimization for 2.5D ICs
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
[Show abstract]
2014 IEEE 32nd VLSI Test Symposium (VTS); 04/2014
Built-in self-test for interposer-based 2.5D ICs
Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik
IEEE International Conference on Computer Design, ICCD 2014
Using 3D-COSTAR for 2.5D test cost optimization
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik
3D Systems Integration Conference (3DIC), 2013 IEEE International; 01/2013
Impact of mid-bond testing in 3D stacked ICs
M. Taouil, S. Hamdioui, E.J. Marinissen, S. Bhawmik
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on; 01/2013
The P1500 DFT disclosure document: a standard to communicate mergeable core DFT data
M.G. Wahl, S. Bhawmik, K. Zarrineh, P. Ghosh, S. Davidson, P. Harrod
Test Conference, 2003. Proceedings. ITC 2003. International; 01/2003
Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access
Mechanism (TAM) Switch.
Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India; 01/2002
Test access methodology for system-on-chip testing
T. J. Chakraborty, S. Bhawmik, C. H Chiang
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme.
Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik
Design Automation Conference, 1999. Proceedings. 36th; 01/1999
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing.
Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik
12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India; 01/1999
A BIST scheme for the detection of path-delay faults
N. Mukherjee, T.J. Chakraborty, S. Bhawmik
Test Conference, 1998. Proceedings, International; 11/1998
An Almost Full-Scan BIST Solution — Higher Fault Coverage and Shorter Test Application
Time (PDF)Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting (Tim) Cheng
IEEE International Test Conference (TC) 10/1998;
A BIST scheme for RTL controller-data paths based on symbolic testability analysis
I. Ghosh, N.K. Jha, S. Bhawmik
Design Automation Conference, 1998. Proceedings; 07/1998
A Hybrid Algorithm For Test Point Selection For Scan-based Bist
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, S. Bhawmik
Design Automation Conference, 1997. Proceedings of the 34th; 07/1997
A practical method for selecting partial scan flip-flops for large circuits
I. Ghosh, S. Bhawmik
VLSI Design, 1997. Proceedings, Tenth International Conference on; 02/1997
PSBIST: A partial-scan based built-in self-test scheme
C.-J. Lin, Y. Zorian, S. Bhawmik
Test Conference, 1993. Proceedings., International; 11/1993
Pascant: a partial scan and test generation system
S. Bhawmik, C.J. Lin, K.-T. Cheng, V.D. Agrawal
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991; 06/1991
Enhanced controllability for IDDQ test sets using partial scan
T.J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, C.J. Lin
Design Automation Conference, 1991. 28th ACM/IEEE; 02/1991
Efficient characterisation of cellular automata
A.K. Das, A. Ganguly, A. Dasgupta, S. Bhawmik, P.P. Chaudhuri
02/1990; DOI:10.1049/ip-e.1990.0008
An integrated CAD environment for design of testable VLSI circuits
Bhawmik, S.; Halder, T.K.; Palchaudhuri, P.
Circuits and Systems, 1988., IEEE International Symposium on
Year: 1988 Pages: 1199 – 1202 vol.2,
Core Based ASIC Design
Higgins, F.; Bhawmik, S.
VLSI Design, 2000. Thirteenth International Conference on Year: 2000