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Professional Experience

Professional Experience

Qualcomm, Bridgewater, NJ                                                                     2007 – Present

Senior Staff Engineer                                                                         

Design and implementation of DFT in Qualcomm ICs. Improved chip quality for Wifi and 4G wireless chips

  • Architected, designed, implemented and validated DFT in multiple SoCs, resulting in high test coverage and low DPPM.
  • Inserted scan and hierarchical test compression (Mentor TestKompress) on Modem blocks and ran ATPG (Fastscan), validating test vectors and resulting in high stuck-at and transition-fault coverage.  
  • Implemented low-pin-count test using Synopsis DFTMAX in mixed analog-digital ICs, achieving high coverage using Synopsis Tetramax ATPG for digital blocks.
  • Implemented Memory BIST using Mentor Tessent suite at RTL and gate level, delivering high memory test coverage.
  • Co-developed core-based test methodology flow, improving test quality and design productivity.
  • Developed test methods for 3D and 2.5D Stacked ICs, resulting in 1 patent (sole author) and multiple co-authored publications.
  • Collaborated with Duke University and TU-DELFT, Netherlands on development of 3D test technology, co-authoring 4 papers published in major conferences and journals.

Conexant Systems, Red Bank, NJ                                                              2005 – 2007 

Principal DFT Engineer                                                                       

Directed overall DFT implementation and test support for DSL and PON chips for location.

  • Architected, designed, implemented and validated DFT (Scan, Memory BIST and Boundary Scan) on 5 large SoCs using Mentor, Synopsys and Logicvision (Mentor Graphics) tools, ensuring high-quality chip production.
  • Ran Tetramax and Fastscan ATPG tools and generated high-quality test patterns, providing very high stuck-at and transition fault coverage.
  • Introduced MemoryBIST implementation in Conexant ICs, improving defect coverage and reducing field returns.
  • Supported test engineers for chip bring-up and test deployment, yielding improvement by diagnosing test failures.
  • Provided leadership to global DFT team and developed company-wide DFT methodology, improving design productivity.

Agere Systems, Allentown, PA                                                            2002 – 2005

Senior Member of Technical Staff                                                              

Provided DFT and BIST solutions and supported ASIC designers.

  • Deployed Logicvision (now Mentor) embedded test technology (logicBIST, memoryBIST) globally, improving test productivity.
  • Trained engineers in the USA, UK, Germany, Singapore and India, supporting designers in implementing DFT technology.

ADDITIONAL EXPERIENCE

Bell Laboratories, Lucent Technologies, Princeton, NJ

Member of Technical Staff                                                                  

Researched and developed DFT and Built-in Self-Test tools. Supported and trained ASIC designers. Collaborated on university research projects.

  • Invented methodology, algorithms and implemented the industry’s first Partial Scan, Partial Scan logic BIST and Testpoint insertion tools, producing high- quality ICs and being granted 4 patents.
  • Managed software developers and supported Lucent chip designers, implementing technology improving test coverage with very little area overhead.
  • Provided marketing support to Bell Labs Design Automation, distributing Scan and BIST tools.
  • Developed and taught IC Testability training course for Lucent Performance and Training Center, resulting in dissemination of Design for Test knowledge and practice.
  • Collaborated with Princeton Univ, Purdue Univ, UC Santa Barbara, Rutgers Univ in multiple DFT research projects, resulting in 3 patents and publications in major research journals and conferences.

Education

Doctor of Philosophy (PhD), Computer Science & Engineering, Indian Institute of Technology, Kharagpur, India

Research Topic – AI Application for Design of Testable Integrated Circuits

Master of Technology, Computer Engineering, Indian Institute of Technology, Kharagpur, India

Bachelor of Technology, Electronics & Electrical Communication Engineering, Indian Institute of Technology,

Kharagpur, India

Professional Affiliations

Member, Secretary and Task Force chair of IEEE 1500 Core Test standards working group

Member of IEEE 1804 Fault Accounting and Coverage standards committee

Keynote and tutorial speaker at several conferences and symposiums

Served as program committee member in multiple conferences.

Senior Member IEEE

Awards

Excellence in Performance Recognition Award, Network IC Division, 2003

Best paper award, 36th Design Automation Conference, 1999

Recognized as Outstanding Asian American Engineer of Lucent/Agere Systems,

Lucent E&ET Customer Service Award, 1998

Best paper award, Computer Society of India, 1988